In a method of fabricating electronic devices from a silicon wafer (hereinafter referred to simply as a “wafer”), a film formation step of forming a conductive film or an insulating film on a surface of the wafer by using CVD (chemical vapor deposition) or the like, a lithography step of forming a photoresist layer in a desired pattern on the formed conductive film or insulating film, and an etching step of forming the conductive film into gate electrodes, or forming wiring grooves or contact holes in the insulating film, by using a plasma produced from processing gas while using the photoresist layer as a mask are repeatedly implemented in that order.
For example, in one electronic device manufacturing method, floating gates formed of a SiN (silicon nitride) layer and a polysilicon layer formed on a wafer are etched by using HBr (hydrogen bromide)-based processing gas, an interlayer SiO2 film below the floating gates is etched by using CHF3-based processing gas, and then a Si layer below the interlayer SiO2 film is etched by using HBr (hydrogen bromide)-based processing gas. In this case, a deposit film 181 made of three layers is formed on side surfaces of trenches (grooves) 180 formed on the wafer (see FIG. 12). The deposit film is made of a SiOBr layer 182, a CF-based deposit layer 183 and a SiOBr layer 184 corresponding to the respective processing gases. The SiOBr layers 182 and 184 are pseudo-SiO2 layers having properties similar to those of a SiO2 layer, and the CF-based deposit layer 183 is an organic material layer.
The SiOBr layers 182 and 184 and the CF-based deposit layer 183 cause problems for the electronic devices such as conduction failures and hence need to be removed.
As a pseudo-SiO2 layer removal method, there is known a substrate processing method in which a wafer is subjected to COR processing (chemical oxide removal) and PHT processing (post heat treatment). The COR processing is a processing in which the pseudo-SiO2 layer is made to undergo chemical reaction with gas molecules to produce a product, and the PHT processing is a processing in which the wafer that has been subjected to the COR processing is heated so as to vaporize and thermally oxidize the product that has been produced on the wafer through the chemical reaction in the COR processing, thereby removing the product from the wafer.
As a substrate processing apparatus for implementing the substrate processing method including COR processing and PHT processing, there is known a substrate processing apparatus having a chemical reaction processing unit and a heat treatment unit connected to the chemical reaction processing unit. The chemical reaction processing unit has a chamber, and carries out the COR processing on a wafer accommodated in the chamber. The heat treatment unit also has a chamber, and carries out the PHT processing on a wafer accommodated in the chamber (see, e.g., specification of U.S. Patent Application Publication No. 2004/0185670).
However, with removing the SiOBr layer 184 as a pseudo-SiO2 layer by using the above substrate processing apparatus, the CF-based deposit layer 183 is exposed. The CF-based deposit layer 183 is not vaporized even upon carrying out the heat treatment, and does not undergo chemical reaction with the gas molecules to produce a product. Therefore, it is difficult to remove the CF-based deposit layer 183 by using the above substrate processing apparatus. That is, it is difficult to efficiently remove the SiOBr layer 184 and the CF-based deposit layer 183.